This invention relates to a method of producing semiconductor devices, and more particularly to a method for consecutively conducting different kinds of processing with processing conditions being changed within a single processing chamber of a plasma device, in which a processing gas used in one plasma processing will not affect the next processing.
As integration and performance of semiconductor devices have been improved, standards of technological requirements of various fine processing techniques have become higher. Particularly in recent years, there are several cases in which different kinds of processing are consecutively conducted within a single chamber of a plasma device, such as in a multi-layer film processing process, a process accompanying on/off switching of an electrostatic chuck, or a process having two-stage dry etching of just etching and over etching for attaining an ultra-high selective ratio.
The electrostatic chuck is a mechanism by which a dc voltage is applied to an internal electrode buried in an insulation member, so as to utilize a Coulomb force generated between the insulation member and a wafer set thereon, for adsorbing and fixing the wafer. For example, in dry etching techniques of recent years, especially in low-temperature etching for carrying out high anisotropic etching under low V.sub.dc (self-bias potential) conditions while limiting reactivity of radicals at a low temperature, it is necessary to level the heat transfer between the wafer stage and the wafer within a plane, so as to limit the in-plane distribution of the etchrate to the minimum level. The electrostatic chuck is highly effective for holding the wafer in such case.
For the electrostatic chuck, there are several different formats depending on whether the wafer is a conductor, a semiconductor or dielectric, and whether the wafer is to be grounded or not. Among these formats, a so-called single electrode format is becoming the mainstream. In this single electrode electrostatic chuck, a dc voltage of predetermined polarity is applied to a single internal electrode in the insulation member, and a facing ground is taken through a processing chamber wall via a plasma. Although having inconvenience that the wafer cannot be adsorbed to the wafer stage in the absence of a plasma, the single electrode electrostatic chuck has a significant advantage of a low possibility that pressure proof of a gate oxide film of a MOS device is deteriorated.
In case the single electrode electrostatic chuck is used, electric charge remains even if the application of the dc voltage is stopped after the plasma processing, Therefore, in order to separate the wafer from the wafer stage, it is necessary to supply a gas which will not substantially affect the result of the plasma processing so as to re-generate the plasma, and then to release the residual charge through the plasma. It is possible to apply to the internal electrode a dc voltage of the polarity opposite to that of the dc used for the wafer adsorption, so as to forcibly remove the residual charge, thereby shortening the time for charge removal. However, excessive application of the voltage induces charge of the opposite polarity, thus re-charging the wafer stage.
In order to solve this problem, a technique of eliminating the charge to a certain extent by applying to the internal electrode a voltage of polarity opposite to that of the voltage used for wafer adsorption after the plasma processing, so as to separate the wafer, and then perfectly removing the residual charge through electric discharge processing using an inactive gas, is disclosed in the JP Patent KOKAI Publication Serial No.4-51642.
On the other hand, with ultra high-selective etching, it is often the case that the etching process for a material layer to be etched is divided into two stages, that is, a just etching process which continues shortly before the underlying material layer is substantially exposed, and an over etching process for etching a residual portion of the material layer to be etched.
A typical example for this two-stage etching is gate electrode processing for a MOS transistor, and more particularly, is the etching of a polysilicon layer or a tungsten polycide film on a gate oxide film consisting of SiO.sub.2. In this gate electrode processing, high selectivity for a thin gate oxide film having a thickness of only about 10 mm must be achieved, while shortening duration of the entire process. For this reason, in a typical process example, high rate etching is carried out using F* as the main etchant in the just etching process, and high-selective etching is carried out using Br* as the main etchant in the over etching process.
The cases in which the different processes are consecutively carried out have been described, such as, the process of residual charge removal after the predetermined plasma processing for the wafer on the single electrode electrostatic chuck, arc the process of consecutively carrying out the just etching and the over etching. As the required standards for the fine processing increases, a problem of adverse effects of a residual gas in one process of plasma processing on the next process has been noted. That is, the problem is a reduction in shape anisotropy and underlying layer selectivity, due to the residual gas or a chemical species formed through reaction of the residual gas and a gas used in the next process.
First, the deterioration of the shape anisotropy is described, using an example of a process of residual charge removal after etching an underlying resist layer in a three-layer resist process, with reference to FIGS. 1A to 1C.
Referring to FIG. 1A, a wafer 54 is set on a single electrode electrostatic chuck 51 on a wafer stage 55 of a magnetically-enhanced microwave plasma etcher, and an underlying resist layer, not shown, on the wafer 54 is etched by using O.sub.2 plasma. Although the wafer stage 55, the single electrode electrostatic chuck 51 and the wafer 54 are described as being separated from one another in FIG. 1A as a matter of convenience for schematic expression, the three parts are actually adhered to one another.
The single electrode electrostatic chuck 51 has a constitution in which a single internal electrode 53 is buried in an insulation member 52. A dc power source 59 capable of applying a positive dc voltage and a dc power source 60 capable of applying a negative dc voltage are connected, in parallel to each other, to the internal electrode 53 via a high frequency cutting filter 57 and a changeover switch 58. These dc power sources 59 and 60 are commonly grounded. In FIG. 1A, as the dc power source 60 is connected to the internal electrode 53, the internal electrode 53 is negatively charged. Consequently, the positive charge is induced to the surface of the insulation member 52, while the negative charge is induced to the surface of the wafer 54. The wafer 54 is adsorbed and held on the single electrode electrostatic chuck 51 by a Coulomb force between the negative charge of the wafer 54 itself and the positive charge of the surface of the insulation member 52. The facing ground is taken through a chamber wall, not shown, via O.sub.2 plasma.
On the other hand, a cooling pipe 56 is buried in the wafer stage 55, so that the wafer 54 is cooled to a predetermined temperature by circulating an appropriate coolant in the cooling pipe 56. Also, an RF power source 63 is connected to the wafer stage 55 via a switch 61 and a blocking capacitor 62 for cutting off dc components.
During the etching, the switch 61 is turned on to apply an RF bias, thus producing a predetermined incident ion energy. This is because the underlying resist layer is etched on the basis of an isotropic burning reaction using oxygen radicals (O*) as the etchant, generating the necessity for securing shape anisotropy by ion assistance effects.
After etching the underlying resist layer, the process of residual charge removal is conducted. In this process, since the RF bias is not applied for securing sufficient underlying layer selectivity, the switch 61 is turned off to separate the RF power source 63 while the dc power source 59 is connected to the internal electrode 53 by operating the changeover switch 58, so as to apply a positive dc voltage, as shown in FIG. 1B. Thus, the charges on the surfaces of the internal electrode 53, the insulation member 52 and the wafer 54 are reduced.
In this case, however, since the application of the RF bias is stopped, O* randomly moving in the plasma dominates. Therefore, the sidewall surface of the pattern of the underlying resist layer which is anisotropically processed by O* is attacked and is isotropically etched.
Ultimately, the changeover switch 58 is turned off as shown in FIG. 1C, and an inactive gas such as Ar is introduced into the processing chamber. Then, the residual charge is perfectly removed by using a plasma formed on dissociation due to electric discharge of the inactive gas.
The above-described is an example in which shape anisotropy is lowered by residual O* in the residual charge removal process. There is also an example of adverse effects of another residual chemical species, in which selectivity for the gate oxide film in lowered, by a residual portion of F* in the just etching, in the over etching of the two-stage etching for gate electrode processing.
There is also an example of adverse effects of a chemical species formed by a reaction between the residual gas and a gas used in the next processing, in which underlying layer selectivity is lowered after the processing a connecting hole. A typical process of hole processing is to etch an SiO.sub.2 interlayer insulation film using a fluorocarbon based gas. If O.sub.2 is introduced shortly after this etching for the purpose of removing the residual charge, dissociation of the residual fluorocarbon based gas is facilitated, so as to increase the F* density in the plasma, thereby lowering underlying layer selectivity.